Physical Design Tools | IC Layout Software

Zeni Physical Design Tool (Zeni PDT) is a fully hierarchical, multi-window, full-custom IC layout editing environment. It supports the physical implementation of custom digital, analog and mixed-signal designs at the device, cell, block and full chip levels. It also offers support for physical design debugging and verification by embedded physical verification tools. Furthermore, it can load third-party verification error files and display violations on the layout and schematic.

Multi-Window Editing

Zeni PDT provides a multi-window co-editing feature. Designers can open more than one layout window for the same or different cellviews. This feature enables you to move or copy objects from one layout cellview to others (see demo), or edit part of a cellview (zoom in) in one window while keeping an eye on the entire design in another window (see demo).

Bird's Eye View

Birds-eye view is a mini window showing the current layout cellview's panorama. Selecting an area in birds-eye view will show the corresponding part of the cellview in the layout editor window, and vice versa. It improves the design efficiency significantly and is highly praised by our customers (see demo).

Cross Select

Cross Select is the key feature for the communication between the Zeni schematic editor and physical design tool. If designers select pins or instances in the schematic window or physical design window, the corresponding objects will be shown automatically in the other window (see demo).

Trace Net

Tracing net connectivity in large-scale hierarchical physical layout designs is a complicated, arduous and painful task, and sometimes it is almost unrealistic. The Trace Net feature will help designers locate and highlight net connectivity hierarchically and automatically with up to 6 different colors (see demo).

Schematic Driven Layout

Schematic Driven Layout is an advanced feature that directly generates the physical layout from schematic cellview or CDL netlist using Vcells or existing layout cellviews. It automatically generates and retains the original hierarchy and connectivity from the schematic, connects pins with flight lines, and places instances with three modes available: Schematic Driven, Square and Line.

Vcells

Vcells, or variable cells, are used to describe programmable devices. They are defined using a Tcl script and Zeni’s object creation commands including rectangle, polygon, pin, and instance. The layout of basic cells and devices can be automatically generated using Vcells. Designers can also modify the parameters of Vcells as needed from within the GUI, enabling them to create and optimize layout designs quickly and efficiently.

Real Time DRC

In traditional design flows, Design Rule Checks (DRC) are generally performed after completing the layout design. The drawback with that is that one rule violation created in the early stage of a design might cause a lot of derived errors in later stages. This can be avoided if DRC errors can be detected as soon as they occur. Zeni PDT’s real time DRC is capable of checking and highlighting design rule violations during layout design, and can significantly reduces the chance of DRC errors during later stages of the design cycle.

Command Line / Run Script

In addition to menus and programmable hot-keys, Zeni PDT allows customers to use the Command Line or Run Script mode to create objects. Command Line enables designers to create objects by typing commands in the prompt line at the bottom of Physical Design Tool window. Designers can also write all commands into an ASCII file and use Run Script to create all objects together.

Generate Array

Unlike instance arrays, the Generate Array feature can use different units for array generation. It is especially useful for memory design. Every unit generated is independent and can be modified individually.

Generate Slot

Zeni PDT provides the feature to generate slots in wide metal wires, as required for stress relief.

Pad Text

This feature allows users to add text labels or pins on top of pad openings, by providing the text, the starting pad and the direction (clockwise or counterclockwise).

Online Layout Verification

Layout verification is a critical step in full custom IC design. Zeni PDT provides a complete set of verification tools including DRC, ERC, LVS, PE and SI. These tools are fully integrated into Zeni PDT and can be directly used to verify and debug physical designs. In addition, Zeni also provides hierarchical DRC and LVS tools that are also integrated into the physical design environment.

Interface with Third Party Tools

Zeni PDT supports the import/export of most industry standard file formats, including GDSII, CIF, LEF, DEF and Cadence technology files. Zeni can also import the command files and result files of Dracula, Calibre, Hercules and Assura.

Email us with any other questions you may have: info(at)zeni-eda.com